1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for stabilizing an interlevel dielectric layer.
2. Description of the Related Art
In general, as semiconductor devices become more integrated, the steps on such semiconductor substrates become larger. The steps cause diffused reflection during a photolithography process, and thus a desired pattern may not be obtained. An interlevel dielectric layer having a high degree of planarization is therefore desirable.
Also, the planarization of the interlevel dielectric layer improves step coverage of a conductive layer to be formed thereon and allows the use of a wider range of thicknesses and line widths of underlying conductive layers.
A phospho-silicate glass (PSG) layer, a boro-phospho-silicate glass (BPSG) layer and an undoped silicate glass (USG) layer, which are formed by a CVD process, are typically used for the interlevel dielectric layer. Since these layers are porous in comparison with a thermal oxide film, humidification can occur in these layers during subsequent processes. When these humidified layers are used for the interlevel dielectric layer, hot carriers are degraded by --OH groups in the interlevel dielectric layer, thereby deteriorating the reliability of the semiconductor device. Also, the dielectric constant of an interlevel dielectric layer increases proportional to humidity, which causes delayed signal transmission or noise.
Also, a chemical mechanical polishing (CMP) process, which is widely used as a global planarization method, may be adapted to planarize an interlevel dielectric layer. Humidification after the CMP process may increase if the interlevel dielectric layer is not hard enough. In addition, defects such as scratches can occur during the CMP process.
Conventionally, an interlevel dielectric layer is first formed, and then cured with high temperature treatment of 800.degree. C. or more to prevent humidification of the interlevel dielectric layer. A semiconductor memory device with a storage capacity of 256 Mb or more employs a dielectric material having a high dielectric constant such as TaO or BST. When a dielectric material layer having a high dielectric constant is formed on a semiconductor substrate, the semiconductor substrate can not tolerate the high temperature heat treatment.
Accordingly, a need exists for a method to prevent humidification in a low temperature process.